1) Field of the Invention
This invention relates generally to fabrication of metal lines in semiconductor devices and more particularly to the fabrication of metal lines using a damascene chemical-mechanical polish process that prevents dishing.
2) Description of the Prior Art
Low resistivity metal such as aluminum and cooper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metal include Al.sub.x Cu.sub.y, ternary alloys Al--Pd--Cu, and Al--Pd--Ni and Al--Cu--Si and other similarly low resistivity metal based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacture has led to reliability problems including inadequate isolating, electromigration, and planarization.
Damascene processes using metal filling vias and lines followed by chemical-mechanical polish (CMP) with various Al, Cu, and Cu-based alloys are a key element of wiring technologies for very large-scale system integration. Damascene and dual damascene processes are described C. Y. Chang, S. M. Sze, in ULSI Technology, by The McGraw-Hill Company, INC. copyright 1997, pp. 444-445.
As the inventor's damascene and dual damascene processes have been implemented with soft metals (e.g., metals such as Al--Cu, Cu, alloys of Al etc.) the inventor has found that the CMP process has caused a dishing problem in the top surface of the metal lines. That is the CMP process removed more material in the center of the metal lines that at the edges thus causing an indentation or dishing problem. Preventing this dishing is the main object of this invention.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering: U.S. Pat. No. 5,731,245 (Joshi et al) shows a damascene CMP method using a hard cap layer 30 over a metal layer (Al or Cu). U.S. Pat. No. 5,441,094 (Pasch) shows a CMP process for planarizing trenches. U.S. Pat. No. 5,385,867 (Udea et al.) shows a various Cu or Al wire structures that can be planarized by CMP. U.S. Pat. No. 5,677,244 (Venkatraman) shows a damascene structure using Al or/and Cu that is planarized by CMP.